A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

3D wafer packaging represents a significant component of the total level processing cost. Replacement Chemical Mechanical Polishing (CMP) process step with corresponding dry etch can yield time and cost savings. Incorporating equipment already utilized in integrated during subsequent Through Silicon Via (TSV) reveal step, efficiencies be achieved, overall die yields being maintained. Using technology to treat 200nm rough back-ground silicon surface, smooth surface peak valley roughness less than 6nm is demonstrated. This patented differs from other smoothing techniques that it aims eliminate any visual grind marks rather just reducing roughness. The elimination visible critical later optical inspection where they are falsely identified as defects. quality equivalent CMP processed such, this has been implemented manufacturing replacing step. novel described combines modification followed by reduction an iterative manner produce without post processing.